The present invention relates to a low electrical loss circuit board using a silicon substrate and incorporating multiple levels of patterned conductors.
The use of monocrystalline silicon has been proposed as a circuit board substrate on which circuit conductors are formed and silicon semiconductor chips are mounted and interconnected by the circuit conductors. This is because the monocrystalline silicon substrate is matched in thermal expansion properties to the silicon chips mounted thereon and exhibits a high thermal conductivity, beneficial in removing heat from the chips mounted thereon. A key shortcoming of such monocrystalline silicon circuit boards resides in the fact that readily-available and reasonably-priced monocrystalline silicon typically has a resistivity limited to the range of about 10.sup.-2 to 10.sup.3 ohm-cm. This results in high dielectric and conduction losses for signals transmitted on circuit conductors of the circuit board, resulting in undesirable signal attenuation. The dielectric and conduction losses are particularly acute for signals above about 1 megahertz in frequency.
It, accordingly, is an object of the present invention to provide a silicon circuit board in which dielectric and conduction losses are minimal.
A further object of the invention is to provide a silicon circuit board incorporating multiple levels of patterned conductors.
Another object of the invention is to provide a silicon circuit board in which an inner level of patterned conductors constitutes ground planes for an outer level of patterned conductors.
The objects of the invention are achieved in a silicon circuit board, which, in preferred form, includes an inner substrate layer of monocrystalline silicon, with upper and lower insulative layers disposed on upper and lower surfaces of the substrate layer, respectively. A first, inner level of upper and lower patterned conductors is provided on the upper and lower insulative layers, respectively, these layers preferably constituting ground planes for a second, outer level of patterned conductors. Provided on the first level upper and lower patterned conductors are upper and lower layers of high resistivity, polycrystalline silicon, respectively, over which are provided second level upper and lower patterned conductors, respectively. To provide electrical communication between the first and second level upper conductor patterns, upper conducting feedthroughs are provided which extend through the upper polycrystalline silicon layer; and to provide electrical communication between the first and second level lower patterned conductors, lower conducting feedthroughs are provided which extend through the lower polycrystalline silicon layer.
A third level of patterned conductors may be incorporated into the silicon circuit board of the invention by forming further upper and lower high resistivity, polycrystalline silicon layers on the second level upper and lower patterned conductors, respectively, followed by formation on these further polycrystalline silicon layers of a third level of upper and lower patterned conductors, respectively. The printed-circuit board may incorporate still further levels of patterned conductors by iteratively providing additional polycrystalline silicon layers and additional levels of patterned conductors arranged in the foregoing sequence.